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cmos 8-bit single chip microcomputer description the CXP84120/84124 is a cmos 8-bit single chip micro-computer integrating on a single chip an a/d converter, serial interface, timer/counter, time base timer, capture timer/counter, remote control reception circuit and other servo systems besides the basic configurations of 8-bit cpu, rom, ram, and i/o port. the CXP84120/84124 also provides a power-on reset function and a sleep/stop function that enables lower power consumption. features wide-range instruction system (213 instructions) to cover various types of data ?16-bit arithmetic/multiplication and division/boolean bit operation instructions minimum instruction cycle 400ns at 10mhz operation 122s at 32khz operation incorporated rom capacity 20k bytes (CXP84120) 24k bytes (cxp84124) incorporated ram capacity 624 bytes peripheral functions ?a/d converter 8 bits, 8 channels, successive approximation method (conversion time of 32s/10mhz) ?serial interface sio with 8-bit, 8-stage fifo incorporated for data use (auto transfer for 1 to 8 bytes), 1 channel 8-bit standard sio, 1 channel ?timer 8-bit timer 8-bit timer/counter 19-bit time base timer 16-bit capture timer/counter 32khz timer/counter ?remote control reception circuit incorporated noise elimination circuit incorporated 8-bit, 6-stage fifo for measurement data ?pwm output 14 bits, 1 channel interruption 14 factors, 15 vectors, multi-interruption possible standby mode sleep/stop package 80-pin plastic qfp piggyback/evaluation chip cxp84100 80-pin ceramic qfp structure silicon gate cmos ic ?1 e92234a81-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. CXP84120/84124 80 pin qfp (plastic)
? 2 CXP84120/84124 8 2 2 2 2 p a 0 / a n 0 t o p a 7 / a n 7 p e 4 / p w m p e 2 / r m c p b 1 / c s 0 p b 3 / s i 0 p b 4 / s o 0 p b 2 / s c k 0 p b 6 / s i 1 p b 7 / s o 1 p b 5 / s c k 1 p e 5 / t o p b 0 / c i n t p e 1 / e c 1 p e 0 / e c 0 a / d c o n v e r t e r a v s s a v r e f 1 4 b i t p w m g e n e r a t o r r e m o c o n f i f o s e r i a l i n t e r f a c e u n i t 0 f i f o s e r i a l i n t e r f a c e u n i t 1 8 b i t t i m e r / c o u n t e r 0 8 b i t t i m e r 1 1 6 b i t c a p t u r e t i m e r / c o u n t e r 2 i n t e r r u p t c o n t r o l l e r p i 0 / i n t 0 p i 1 / i n t 1 p i 2 / i n t 2 p i 3 / i n t 3 p e 3 / n m i s p c 7 0 0 c p u c o r e r o m 2 0 k b y t e s ( c x p 8 4 1 2 0 ) 2 4 k b y t e s ( c x p 8 4 1 2 4 ) c l o c k g e n . / s y s t e m c o n t r o l r a m 6 2 4 b y t e s p r e s c a l e r / t i m e b a s e t i m e r e x t a l x t a l v d d v s s p o r t a 7 8 8 4 2 8 p a 0 t o p a 7 p b 0 t o p b 6 p b 7 p c 0 t o p c 7 p d 0 t o p d 7 p e 0 t o p e 3 p e 4 t o p e 5 p f 0 t o p f 7 p g 0 t o p g 7 p i 0 t o p i 7 r s t 8 8 8 p o r t b p o r t c p o r t d p o r t e p o r t f p o r t g p o r t i t e x t x p h 0 t o p h 7 8 p o r t h 3 2 k h z t i m e r / c o u n t e r block diagram
? 3 CXP84120/84124 pin assignment (top view) p f 3 p f 4 p f 5 p f 6 p f 7 p d 0 p d 1 p d 2 p d 3 p d 4 p d 5 p d 6 p d 7 p c 0 p c 1 p c 2 p c 3 p c 4 p c 5 p c 6 p c 7 p h 0 p h 1 p h 2 p i 4 p i 3 / i n t 3 p i 2 / i n t 2 p i 1 / i n t 1 p i 0 / i n t 0 p e 5 t o p e 4 / p w m p e 3 / n m i p e 2 / r m c p e 1 / e c 1 p e 0 / e c 0 p b 7 / s o 1 p b 6 / s i 1 p b 5 / s c k 1 p b 4 / s o 0 p b 3 / s i 0 p b 2 / s c k 0 p b 1 / c s 0 p b 0 / c i n t p a 7 / a n 7 p a 6 / a n 6 p a 5 / a n 5 p a 4 / a n 4 p a 3 / a n 3 p h 3 p h 4 p h 5 p h 6 p h 7 r s t e x t a l x t a l v s s t x t e x a v s s a v r e f p a 0 / a n 0 p a 1 / a n 1 p a 2 / a n 2 p f 2 p f 1 p f 0 p g 7 p g 6 p g 5 p g 4 n c v d d p g 3 p g 2 p g 1 p g 0 p i 7 p i 6 p i 5 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 1 3 2 3 3 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 7 0 6 9 6 8 6 7 6 3 6 4 6 5 6 6 6 1 6 2 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 8 0 1 note) nc (pin 73) must be connected to v dd .
? 4 CXP84120/84124 pin description symbol i/o description i/o/analog input pa0/an0 to pa7/an7 (port a) 8-bit i/o port. i/o can be set in a unit of single bit. incorporation of the pull-up resistance can be set through the software in a unit of 4 bits. (8 pins) analog inputs to a/d converter. (8 pins) i/o pc0 to pc7 (port c) 8-bit i/o port. i/o can be set in a unit of single bit. capable of driving 12ma sink current. incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) i/o pd0 to pd7 (port d) 8-bit i/o port. i/o can be set in a unit of single bits. incorporation of pull- up resistor can be set through the software in a unit of 4 bits. (8 pins) i/o pf0 to pf7 (port f) 8-bit i/o port. i/o can be set in a unit of single bit. incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) input/input input/input input/input input/input output/output output/output/ output pe0/ec0 pe1/ec1 pe2/rmc pe3/nmi pe4/pwm pe5/to/adj (port e) 6-bit port. lower 4 bits are for inputs; upper 2 bits are for outputs. (6 pins) external event inputs for timer/counter. (2 pins) remote control reception circuit input. non-maskable interruption request input. 14-bit pwm output. rectangular wave output for 16-bit timer/counter. output for 32khz oscillation frequency division. i/o/input i/o/input i/o/i/o i/o/input i/o/output i/o/i/o i/o/input output/output pb0/cint pb1/cs0 pb2/sck0 pb3/si0 pb4/so0 pb5/sck1 pb6/si1 pb7/so1 (port b) 7-bit i/o port in which i/o can be set in a unit of single bit. also, an uppermost bit (pb7) exclusively for output. incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) external capture input to 16-bit timer/counter. chip select input for serial interface (ch0). serial clock i/o (ch0). serial data input (ch0). serial data output (ch0). serial clock i/o (ch1). serial data input (ch1). serial data output (ch1).
? 5 CXP84120/84124 symbol i/o description i/o pg0 to pg7 (port g) 8-bit i/o port. i/o can be set in a unit of single bits. incorporation of pull- up resistor can be set through the software in a unit of 4 bits. (8 pins) i/o ph0 to ph7 (port h) 8-bit i/o port. i/o can be set in a unit of single bits. incorporation of pull- up resistor can be set through the software in a unit of 4 bits. (8 pins) i/o/input pi0/int0 to pi3/int3 i/o pi4 to pi7 input crystal connectors for system clock oscillation. when the clock is supplied externally, input to extal; opposite phase clock should be input to xtal. extal output xtal input crystal connectors for 32khz timer/counter clock generation circuit. connect a 32khz crystal oscillator between tex and tx. for usage as event input, connect clock oscillation source to tex, and open tx. tex output tx input low-level active, system reset. rst nc. under normal operating conditions, connect to v dd . nc input reference voltage input for a/d converter. av ref a/d converter gnd. avss positive power supply. v dd gnd vss (port i) 8-bit i/o ports. i/o can be set in a unit of single bit. incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) external interruption request inputs.
? 6 CXP84120/84124 port b d a t a b u s r d ( p o r t b ) a a a a a a a a a a a a p o r t b d i r e c t i o n i p a a a a a a p o r t b d a t a a a a a a a a a p u l l - u p r e s i s t a n c e " 0 " w h e n r e s e t " 0 " w h e n r e s e t * p u l l - u p t r a n s i s t o r s a p p r o x . 1 0 k w * s c h m i t t i n p u t c i n t c s 0 s i 0 s i 1 8 pins hi-z hi-z when reset pa0/an0 to pa7/an7 pb0/cint pb1/cs0 pb3/si0 pb6/si1 port b 4 pins 2 pins hi-z pb2/sck0 pb5/sck1 d a t a b u s r d ( p o r t a ) a a a a a a a a a a p o r t a d i r e c t i o n i p a a a a a p o r t a d a t a a a a a a a p u l l - u p r e s i s t a n c e a a a a a a p o r t a i n p u t s e l e c t i o n i n p u t p r o t e c t i o n c i r c u i t " 0 " w h e n r e s e t " 0 " w h e n r e s e t " 0 " w h e n r e s e t i n p u t m u l t i p l e x e r a / d c o n v e r t e r * p u l l - u p t r a n s i s t o r s a p p r o x . 1 0 k w * input/output circuit formats for pins port a pin circuit format d a t a b u s r d ( p o r t b ) a a a a i p a a a a a a a a a a p o r t b o u t p u t s e l e c t i o n " 0 " w h e n r e s e t * p u l l - u p t r a n s i s t o r s a p p r o x . 1 0 k w * s c h m i t t i n p u t s c k i n a a a a p o r t b d a t a a a a a p o r t b d i r e c t i o n " 0 " w h e n r e s e t a a a a a a a a p u l l - u p r e s i s t a n c e " 0 " w h e n r e s e t s c k o u t o u t p u t e n a b l e
? 7 CXP84120/84124 1 pin hi-z hi-z pin when reset circuit format pb4/so0 pc0 to pc7 8 pins 4 pins hi-z pe0/ec0 pe1/ec1 pe2/rmc pe3/nmi a a a a i p a a a a s c h m i t t i n p u t r d ( p o r t e ) d a t a b u s e c 0 e c 1 r m c / n m i d a t a b u s r d ( p o r t c ) a a a a a a a a a a p o r t c d i r e c t i o n i p a a a a a a a a a a a a p o r t c d a t a a a a a p u l l - u p r e s i s t a n c e " 0 " w h e n r e s e t " 0 " w h e n r e s e t * 1 l a r g e c u r r e n t d r i v e o f 1 2 m a p o s s i b l e * 2 p u l l - u p t r a n s i s t o r s a p p r o x . 1 0 k w * 2 * 1 d a t a b u s r d ( p o r t b ) a a a a i p a a a a a a a a a a p o r t b o u t p u t s e l e c t i o n " 0 " w h e n r e s e t * p u l l - u p t r a n s i s t o r s a p p r o x . 1 0 k w * a a a a p o r t b d a t a a a a a p o r t b d i r e c t i o n " 0 " w h e n r e s e t a a a a a a a a p u l l - u p r e s i s t a n c e s o o u t p u t e n a b l e port e port c port b 1 pin high level pb7/so1 d a t a b u s r d ( p o r t b ) a a " 1 " w h e n r e s e t * p u l l - u p t r a n s i s t o r s a p p r o x . 1 0 k w a a a a a a a a p o r t b o u t p u t s e l e c t i o n a a a a a a a a p o r t b d a t a o u t p u t e n a b l e s o i n t e r n a l r e s e t s i g n a l * port b
? 8 CXP84120/84124 1 pin high level pin when reset circuit format pe5/to/adj d a t a b u s a a a a a a a a p o r t e o u t p u t s e l e c t i o n " 0 " w h e n r e s e t a a a a a a p o r t e d a t a " 1 " w h e n r e s e t r d ( p o r t e ) * a d j s i g n a l s a r e f r e q u e n c y d i v i s i o n o u t p u t s f o r 3 2 k h z o s c i l l a t i o n f r e q u e n c y a d j u s t m e n t . a d j 2 k p r o v i d e s u s a g e a s b u z z e r o u t p u t . a a a p o r t e o u t p u t s e l e c t i o n " 0 0 " w h e n r e s e t a a a a a a p o r t e o u t p u t s e l e c t i o n a a a a o u p u t e n a b l e t o a d j 1 6 k a d j 2 k m p x port e 1 pin high level pe4/pwm d a t a b u s r d ( p o r t e ) a a a a a a a a a a a a p o r t e o u t p u t s e l e c t i o n p w m a a a a a a a a p o r t e d a t a " 0 " w h e n r e s e t " 1 " w h e n r e s e t port e 36 pins hi-z pd0 to pd7 pf0 to pf7 pg0 to pg7 ph0 to ph7 pi4 to pi7 d a t a b u s r d a a a a i p a a a a a a a a a a p o r t d a t a " 0 " w h e n r e s e t * p u l l - u p t r a n s i s t o r s a p p r o x . 1 0 k w * a a a a a a a a p o r t d i r e c t i o n a a a a a a a a p u l l - u p r e s i s t a n c e " 0 " w h e n r e s e t port d port f port g port h port i
? 9 CXP84120/84124 2 pins oscillation pin when reset circuit format extal xtal a a a a a a i p a a a a e x t a l x t a l d i a g r a m s h o w s c i r c u i t c o m p o s i t i o n d u r i n g o s c i l l a t i o n . f e e d b a c k r e s i s t o r i s r e m o v e d d u r i n g s t o p . a a a a i p 2 pins oscillation tex tx a a a a a a i p a a a a t e x d i a g r a m s h o w s c i r c u i t c o m p o s i t i o n d u r i n g o s c i l l a t i o n . a a a a i p w h e n t h e o p e r a t i o n o f t h e o s c i l l a t i o n c i r c u i t i s s t o p p e d b y t h e s o f t w a r e , t h e f e e d b a c k r e s i s t o r i s r e m o v e d , a n d t e x a n d t x b e c o m e " l o w " l e v e l a n d " h i g h " l e v e l r e s p e c t i v e l y . t x 1 pin low level rst a a s c h m i t t i n p u t p u l l - u p r e s i s t o r m a s k o p t i o n o p a a i p 4 pins hi-z d a t a b u s r d a a a a i p a a a a a a a a a a p o r t d a t a " 0 " w h e n r e s e t * p u l l - u p t r a n s i s t o r s a p p r o x . 1 0 k w * a a a a a a a a p o r t d i r e c t i o n a a a a a a a a p u l l - u p r e s i s t a n c e " 0 " w h e n r e s e t i n t 0 i n t 1 i n t 2 i n t 3 port i pi0/int0 to pi3/int3
? 10 CXP84120/84124 input voltage output voltage high level output current high level total output current low level total output current operating temperature storage temperature allowable power dissipation * 1 v in and v out must not exceed v dd + 0.3v. * 2 the large current drive transistor is the n-ch transistor of port c (pc). note) usage exceeding absolute maximum ratings may permanently impair the lsi. normal operation should be conducted under the recommended operating conditions. exceeding these conditions may adversely affect the reliability of the lsi. v dd av ss v in v out i oh i oh i ol i olc i ol topr tstg p d low level output current supply voltage ?.3 to +7.0 ?.3 to +0.3 ?.3 to +7.0 * 1 ?.3 to +7.0 * 1 ? ?0 15 20 100 ?0 to +75 ?5 to +150 600 v v v v ma ma ma ma ma c c mw output per pin total for all output pins value per pin, excluding large current outputs value per pin * 2 for large current outputs total for all output pins item symbol rating unit remarks absolute maximum ratings (vss = 0v reference) high level input voltage low level input voltage operating temperature supply voltage 5.5 5.5 5.5 5.5 v dd v dd v dd + 0.3 0.3v dd 0.2v dd 0.4 +75 v v v v v v c v item symbol min. max. unit remarks 4.5 3.5 2.7 2.5 0.7v dd 0.8v dd v dd ?0.4 0 0 ?.3 ?0 v ih v ihs v ihex v il v ils v ilex topr high-speed mode guaranteed operation range * 1 low-speed mode guaranteed operation range * 1 guaranteed operation range with tex clock guaranteed data hold range during stop * 2 hysteresis input * 3 extal * 4 * 2 hysteresis input * 3 extal * 4 v dd recommended operating conditions (vss = 0v reference) * 1 high-speed mode is 1/2 frequency division clock selection; low-speed mode is 1/16 frequency division clock selection. * 2 value for each pin of normal input ports (pa, pb3, pb4, pb6, pc, pd, pf to ph, pi4 to pi7). * 3 value of the following pins: rst, cint, cs0, sck0, sck1, ec0, ec1, rmc, nmi, int0, int1, int2, int3. * 4 specifies only during external clock input.
? 11 CXP84120/84124 v dd = 4.5v, i oh = ?.5ma v dd = 4.5v, i oh = ?.2ma v dd = 4.5v, i ol = 1.8ma v dd = 4.5v, i ol = 3.6ma v dd = 4.5v, i ol = 12.0ma v dd = 5.5v, v ih = 5.5v v dd = 5.5v, v il = 0.4v v dd = 5.5v, v ih = 5.5v high level output voltage 4.0 3.5 0.5 ?.5 0.1 ?.1 ?.5 ?0 v v v v v a a a a a ma a a pc pa to pd, pe4, pe5, pf to pi extal tex rst * 1 item symbol pins conditions min. clock 1mhz 0v for all pins excluding measured pins v dd i dd1 i il i iz i dd2 i dds1 i dds2 i dds3 c in v oh v ol i ihe i ile i iht i ilt i ilr low level output voltage input current typ. 0.4 0.6 1.5 40 ?0 10 ?0 ?00 ?.0 10 max. unit dc characteristics electrical characteristics (ta = ?0 to +75 c, vss = 0v reference) * 1 rst specifies the input current when pull-up resistance has been selected; leakage current when no resistance has been selected. * 2 pins pa to pd, and pf to pi specify the input current when pull-up resistance has been selected; leakage current when no resistance has been selected. (excludes output pb7) * 3 when all pins are open. v dd = 5.5v, 10mhz crystal oscillation (c 1 = c 2 = 15pf) v dd = 3v, 32khz crystal oscillation (c 1 = c 2 = 47pf) v dd = 5.5v, 10mhz crystal oscillation (c 1 = c 2 = 15pf) v dd = 3v, 32khz crystal oscillation (c 1 = c 2 = 47pf) v dd = 5.5v, t ermination of 10mhz and 32khz crystal oscillation power supply current * 3 input capacity v dd = 5.5v, v il = 0.4v v dd = 4.5v, v il = 4.0v v dd = 5.5v, v i = 0, 5.5v high-speed mode operation (1/2 frequency division clock) sleep mode stop mode i/o leakage current pa to pd * 2 , pf to pi * 2 pe0 to pe3, rst * 1 40 100 8 10 30 18 35 1.1 9 ma a ma a pf 20 10 a pins other than pb7, pe4, pe5, av ref , av ss , v dd , v ss
? 12 CXP84120/84124 e x t a l t x h t x l t c f t c r 0 . 4 v v d d 0 . 4 v 1 / f c a a a a a a a a a a a a a a a a a a a a a a a a a a a c r y s t a l o s c i l l a t i o n c e r a m i c o s c i l l a t i o n e x t a l x t a l e x t e r n a l c l o c k e x t a l x t a l 7 4 h c 0 4 c 1 c 2 a a a a a a a a a a a a 3 2 k h z c l o c k a p p l i e d c o n d i t i o n c r y s t a l o s c i l l a t i o n t e x t x c 1 c 2 fig. 2. clock applied conditions fig. 1. clock timing ac characteristics (1) clock timing (ta = ?0 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) * 1 t sys indicates the three values below according to the upper two bits (cpu clock selection) of the clock control register (address: 00fe h ). t sys [ns] = 2000/fc (upper two bits = ?0?, 4000/fc (upper two bits = ?1?, 16000/fc (upper two bits = ?1? system clock frequency system clock input pulse width system clock input rise time, fall time event count input clock pulse width event count input clock rise time, fall time system clock frequency event count input clock input pulse width event count input clock rise time, fall time f c t xl , t xh t cr , t cf t eh , t el t er , t ef f c t tl , t th t tr , t tf xtal extal extal extal ec0 ec1 ec0 ec1 tex tx tex tex mhz ns ns ns ms khz s ms item symbol pins conditions min. unit fig. 1, fig. 2 fig. 1, fig. 2 external clock drive fig. 1, fig. 2 external clock drive fig. 3 fig. 3 v dd = 2.7 to 5.5v fig. 2 (32khz clock applied condition) fig. 3 fig. 3 1 37.5 t sys + 50 * 1 10 typ. 32.768 max. 10 200 20 20
? 13 CXP84120/84124 chip select transfer mode (sck0 = output mode) chip select transfer mode (sck0 = output mode) chip select transfer mode chip select transfer mode chip select transfer mode (2) serial transfer (ch0) (ta = ?0 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) item cs0 ? sck0 delay time cs0 - ? sck0 float delay time cs0 ? so0 delay time cs0 - ? so0 float delay time cs0 high level width sck0 cycle time sck0 high, low level width si0 input setup time (for sck0 - ) si0 input hold time (for sck0 - ) sck0 ? so0 delay time t dcsk t dcskf t dcso t dcsof t whcs t kcy t kh , t kl t sik t ksi t kso sck0 sck0 so0 so0 cs0 sck0 sck0 si0 si0 so0 input mode output mode input mode output mode sck0 input mode sck0 output mode sck0 input mode sck0 output mode sck0 input mode sck0 output mode ns ns ns ns ns symbol pin min. t sys + 200 t sys + 200 t sys + 200 t sys + 200 t sys + 200 2 t sys + 200 16000/fc t sys + 100 8000/fc ?50 100 200 t sys + 200 100 ns ns ns ns ns ns ns ns ns ns t sys + 200 100 max. unit condition note 1) t sys indicates the three values below according to the upper two bits (cpu clock selection) of the clock control register (address: 00fe h ). t sys [ns] = 2000/fc (upper two bits = ?0?, 4000/fc (upper two bits = ?1?, 16000/fc (upper two bits = ?1? note 2) the load condition for the sck0 output mode, so0 output delay time is 50pf + 1ttl. t e x e c 0 e c 1 t e h t e l t e f t e r 0 . 2 v d d 0 . 8 v d d t t h t t l t t f t t r fig. 3. event count clock timing
c s 0 s c k 0 0 . 2 v d d 0 . 8 v d d t w h c s t d c s k t d c s k f 0 . 8 v d d 0 . 2 v d d 0 . 8 v d d t k c y t k l t k h 0 . 8 v d d 0 . 2 v d d s i 0 t s i k i n p u t d a t a t d c s o t k s o t d c s o f o u t p u t d a t a 0 . 8 v d d 0 . 2 v d d s o 0 t k s i ? 14 CXP84120/84124 fig. 4. serial transfer ch0 timing
? 15 CXP84120/84124 fig. 5. serial transfer ch1 timing s c k 1 s i 1 s o 1 t k c y t k l t k h 0 . 2 v d d 0 . 8 v d d t s i k t k s i t k s o i n p u t d a t a o u t p u t d a t a 0 . 2 v d d 0 . 8 v d d 0 . 2 v d d 0 . 8 v d d serial transfer (ch1) (ta = ?0 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) item symbol pin min. max. unit condition t kcy t kh , t kl t sik t ksi t kso sck1 sck1 si1 si1 so1 input mode output mode input mode output mode sck1 input mode sck1 output mode sck1 input mode sck1 output mode sck1 input mode sck1 output mode 1000 16000/fc 400 8000/fc ?50 100 200 200 100 200 100 ns ns ns ns ns ns ns ns ns ns note) the load condition for the sck1 output mode, so1 output delay time is 50pf + 1ttl. sck1 cycle time sck1 high, low level width si1 input setup time (for sck1 - ) si1 input hold time (for sck1 - ) sck1 ? so1 delay time
? 16 CXP84120/84124 fig. 6. definition of a/d converter terms a n a l o g i n p u t l i n e a r i t y e r r o r v f t v z t 0 0 h 0 1 h f e h f f h d i g i t a l c o n v e r s i o n v a l u e * 1 v z t : v a l u e a t w h i c h t h e d i g i t a l c o n v e r s i o n v a l u e c h a n g e s f r o m 0 0 h t o 0 1 h a n d v i c e v e r s a . * 2 v f t : v a l u e a t w h i c h t h e d i g i t a l c o n v e r s i o n v a l u e c h a n g e s f r o m f e h t o f f h a n d v i c e v e r s a . * 3 f a d c i n d i c a t e s t h e b e l o w v a l u e s d u e t o a d c o p e r a t i o n c l o c k s e l e c t i o n . d u r i n g p s 2 s e l e c t i o n , f a d c = f c / 2 d u r i n g p s 1 s e l e c t i o n , f a d c = f c conversion time sampling time reference input voltage analog input voltage t conv t samp v ref v ian v zt * 1 v ft * 2 i ref av ref an0 to an7 ta = 25 c v dd = 5.0v v ss = av ss = 0v operation mode sleep mode stop mode 32khz operation mode linearity error zero transition voltage full-scale transition voltage resolution av ref current av ref i refs s s v v v dd av ref 1.0 ma 10 a 0.6 160/f adc * 3 12/f adc * 3 v dd ?0.5 0 item symbol pin condition min. typ. max. unit bits (3) a/d converter characteristics (ta = ?0 to +75 c, v dd = 4.5 to 5.5v, av ref = 4.0 to av dd , vss = av ss = 0v reference) 8 lsb 150 mv 5120 70 5050 ?0 4930 mv 5
? 17 CXP84120/84124 (4) interruption, reset input (ta = ?0 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) 0 . 2 v d d 0 . 8 v d d t i h t i l i n t 0 i n t 1 i n t 2 i n t 3 n m i ( n m i s p e c i f i e s o n l y f o r t h e f a l l i n g e d g e . ) t i l t i h fig 7. interruption input timing t r s l 0 . 2 v d d r s t external interruption high, low level width reset input low level width int0 int1 int2 int3 nmi pj0 to pj7 rst 1 8/fc s s item symbol pins condition min. max. unit t ih t il t rsl fig. 8. rst input timing
? 18 CXP84120/84124 appendix c 1 a a a a a a a a a a a a e x t a l x t a l c 2 a a a a a a a a a a a a e x t a l x t a l ( i ) m a i n c l o c k a a a a a a a a a a a a e x t a l x t a l c 1 c 2 x t a l ( i i ) m a i n c l o c k a a a a a a a a a a a a e x t a l x t a l c 1 c 2 r d a a a a a a a a a a a a t e x t x ( i i i ) s u b c l o c k item content reset pin pull-up resistance non-existent existent mask option table manufacturer murata mfg co., ltd. river eletec corporation kinseki ltd. model csa4.19mg csa8.00mg cst4.19mgw * cst8.00mtw * hc-49/u03 hc-49/u (-s) fc (mhz) 4.19 8.00 10.00 4.19 8.00 10.00 4.19 8.00 10.00 4.19 8.00 10.00 30 15 27 30 15 27 c 1 (pf) c 2 (pf) circuit example (i) csa10.0mt (ii) cst10.00mtw * (i) those marked with an asterisk ( * ) signify types with built-in ground capacitance (c 1 , c 2 ). fig. 9. spc700 series recommended oscillation circuit
? 19 CXP84120/84124 package outline unit: mm p a c k a g e s t r u c t u r e s o n y c o d e e i a j c o d e j e d e c c o d e q f p - 8 0 p - l 0 1 q f p 0 8 0 - p - 1 4 2 0 p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s e p o x y r e s i n s o l d e r p l a t i n g 4 2 / c o p p e r a l l o y 1 . 6 g 2 3 . 9 0 . 4 2 0 . 0 0 . 1 + 0 . 4 1 8 0 6 5 6 4 4 1 4 0 2 5 2 4 0 . 8 0 . 3 5 0 . 1 + 0 . 1 5 1 4 . 0 0 . 1 + 0 . 4 1 7 . 9 0 . 4 1 6 . 3 0 . 1 0 . 0 5 + 0 . 2 2 . 7 5 0 . 1 5 + 0 . 3 5 0 . 8 0 . 2 0 . 1 5 0 . 0 5 + 0 . 1 8 0 p i n q f p ( p l a s t i c ) m 0 . 2 0 . 1 5 0 t o 1 0 d e t a i l a a

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